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hy57v281620a 4 banks x 2m x 16bits synchronous dram this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.0/dec.99 description the hyundai hy57v281620a is a 134,217,728bit cmos synchronous dram, ideally suited for the main memory applications which require large memory density and high bandwidth. hy57v281620a is organized as 4banks of 2,097,152x16 hy57v281620a is offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are sync hro- nized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of consecutive read or write cycles ini tiated by a single control command (burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). a b urst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burs t read or write command on any cycle. (this pipelined design is not restricted by a `2n` rule.) features ? single 3.3 0.3v power supply ? all device pins are compatible with lvttl interface ? jedec standard 400mil 54pin tsop-ii with 0.8mm of pin pitch ? all inputs and outputs referenced to positive edge of system clock ? data mask function by udqm or ldqm ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information part no. clock frequency power organization interface package hy57v281620at-6 166mhz normal 4banks x 2mbits x16 lvttl 400mil 54pin tsop ii hy57v281620at-k 133mhz hy57v281620at-h 133mhz hy57v281620at-8 125mhz hy57v281620at-p 100mhz hy57v281620at-s 100mhz hy57v281620at-10 100mhz hy57v281620alt-6 166mhz low power hy57v281620alt-k 133mhz hy57v281620alt-h 133mhz hy57v281620alt-8 125mhz hy57v281620alt-p 100mhz hy57v281620alt-s 100mhz HY57V281620ALT-10 100mhz
hy57v281620a rev. 1.0/dec.99 2 pin configuration pin description pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke, udqm and ldqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a11 address row address : ra0 ~ ra11, column address : ca0 ~ ca8 auto-precharge flag : a10 ras , cas , we row address strobe, col- umn address strobe, write enable ras , cas and we define the operation refer function truth table for details udqm, ldqm data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq15 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for internal circuits and input buffers v ddq /v ssq data output power/ground power supply for output buffers nc no connection no connection v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 v ss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 v dd ldqm /we /cas /ras /cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd 54 pin tsop ii 400mil x 875mil 0.8mm pin pitch
hy57v281620a rev. 1.0/dec.99 3 functional block diagram 2mbit x 4banks x 16 i/o synchronous dram x decoders state machine a0 a1 a11 ba0 ba1 address buffers address registers mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency internal row counter dq0 dq1 dq14 dq15 refresh self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we udqm ldqm 2 mx16 bank 3 x decoders x decoders memory cell array y decoders x decoders 2 mx16 bank 0 2 mx16 bank 1 2 mx16 bank 2
hy57v281620a rev. 1.0/dec.99 4 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. dc operating condition (t a =0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with <=3ns of duration. 3.v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration. ac operating test condition (t a =0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.output load to measure access times is equivalent to two ttl gates and one capacitor (50pf). for details, refer to ac/dc outpu t load circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1 w soldering temperature time t solder 260 10 c sec parameter symbol min typ max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il -0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement c l 50 pf 1
hy57v281620a rev. 1.0/dec.99 5 capacitance (ta=25 c , f=1mhz) output load circuit dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 parameter pin symbol -6/k/h -8/p/s/10 unit min max min max input capacitance clk c i1 2.5 3.5 2.5 4.0 pf a0 ~ a11, ba0, ba1, cke, cs , ras , cas , we , udqm, ldqm ci 2 2.5 3.8 2.5 5.0 pf data input / output capacitance dq0 ~ dq15 c i/o 4.0 6.5 4.0 6.5 pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol - 0.4 v i ol = +4ma vtt =1.4v rt=250 w 50 pf output 50 pf output dc output load circuit ac output load circuit
hy57v281620a rev. 1.0/dec.99 6 dc characteristics ii (ta=0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2.min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3.hy57v281620at-6/k/h/8/p/s/10 4.hy57v281620alt-6/k/h/8/p/s/10 parameter symbol test condition speed unit note -6 -k -h -8 -p -s -10 operating current i dd1 burst length=1, one bank active t rc 3 t rc (min), i ol =0ma 120 110 110 100 100 100 90 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 2 ma i dd2ps cke v il (max), t ck = 2 precharge standby current in non power down mode i dd2n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks. all other pins 3 v dd -0.2v or 0.2v 20 ma i dd2ns cke 3 v ih (min), t ck = input signals are stable. 10 active standby current in power down mode i dd3p cke v il (max), t ck = min 7 ma i dd3ps cke v il (max), t ck = 7 active standby current in non power down mode i dd3n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks. all other pins 3 v dd -0.2v or 0.2v 40 ma i dd3ns cke 3 v ih (min), t ck = input signals are stable. 40 burst mode operating current i dd4 t ck 3 t ck (min), i ol =0ma all banks active cl=3 140 120 120 110 100 100 100 ma 1 cl=2 100 100 100 100 100 100 100 auto refresh current i dd5 t rrc 3 t rrc (min), all banks active 240 220 220 200 200 200 150 ma 2 self refresh current i dd6 cke 0.2v 2 ma 3 800 ua 4
hy57v281620a rev. 1.0/dec.99 7 ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter 2.access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter parameter symbol -6 -k -h -8 -p -s -10 unit note min max min max min max min max min max min max min max system clock cycle time cas latency = 3 tck3 6 1000 7.5 1000 7.5 1000 8 1000 10 1000 10 1000 10 1000 ns cas latency = 2 tck2 10 7.5 10 10 10 12 12 ns clock high pulse width tchw 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - 3 - ns 1 clock low pulse width tclw 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 5.4 - 5.4 - 5.4 - 6 - 6 - 6 - 8 ns 2 cas latency = 2 tac2 - 6 - 5.4 - 6 - 6 - 6 - 6 - 8 ns data-out hold time toh 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - 3 - ns data-input setup time tds 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - 2.5 - ns 1 data-input hold time tdh 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - 1.5 - ns 1 address setup time tas 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - 2.5 - ns 1 address hold time tah 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - 1.5 - ns 1 cke setup time tcks 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - 2.5 - ns 1 cke hold time tckh 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - 1.5 - ns 1 command setup time tcs 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - 2.5 - ns 1 command hold time tch 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - 1.5 - ns 1 clk to data output in low-z time tolz 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns clk to data output in high-z time cas latency = 3 tohz3 2.7 5.4 2.7 5.4 2.7 5.4 3 6 3 6 3 6 3 8 ns cas latency = 2 tohz2 2.7 5.4 2.7 5.4 3 6 3 6 3 6 3 6 3 8 ns
hy57v281620a rev. 1.0/dec.99 8 ac characteristics ii note : 1. a new command can be given trrc after self refresh exit parameter symbol -6 -k -h -8 -p -s -10 unit note min max min max min max min max min max min max min max ras cycle time operation trc 60 - 60 - 65 - 68 - 70 - 70 - 80 - ns auto refresh trrc 60 - 60 - 65 - 68 - 70 - 70 - 96 - ns ras to cas delay trcd 18 - 15 - 20 - 20 - 20 - 20 - 30 - ns ras active time tras 42 100k 45 100k 45 100k 48 100k 50 100k 50 100k 50 100k ns ras precharge time trp 18 - 15 - 20 - 20 - 20 - 20 - 30 - ns ras to ras bank active delay trrd 12 - 15 - 15 - 16 - 20 - 20 - 20 - ns cas to cas delay tccd 1 - 1 - 1 - 1 - 1 - 1 - 1 - clk write command to data-in delay twtl 0 - 0 - 0 - 0 - 0 - 0 - 0 - clk data-in to precharge command tdpl 2 - 2 - 2 - 1 - 1 - 1 - 1 - clk data-in to active command tdal 5 - 4 - 5 - 4 - 3 - 3 - 4 - clk dqm to data-out hi-z tdqz 2 - 2 - 2 - 2 - 2 - 2 - 2 - clk dqm to data-in mask tdqm 0 - 0 - 0 - 0 - 0 - 0 - 0 - clk mrs to new command tmrd 2 - 2 - 2 - 2 - 2 - 2 - 2 - clk precharge to data output hi-z cas latency = 3 tproz3 3 - 3 - 3 - 3 - 3 - 3 - 3 - clk cas latency = 2 tproz2 2 - 2 - 2 - 2 - 2 - 2 - 2 - clk power down exit time tpde 1 - 1 - 1 - 1 - 1 - 1 - 1 - clk self refresh exit time tsre 1 - 1 - 1 - 1 - 1 - 1 - 1 - clk 1 refresh time tref - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms
hy57v281620a rev. 1.0/dec.99 9 ibis specification i oh characteristics (pull-up) i ol characteristics (pull-down) voltage 100mhz (min) 100mhz (max) 66mhz (min) (v) i(ma) i(ma) i(ma) 3.45 -2.4 3.3 -27.3 3.0 0 -74.1 -0.7 2.6 -21.1 -129.2 -7.5 2.4 -34.1 -153.3 -13.3 2.0 -58.7 -197 -27.5 1.8 -67.3 -226.2 -35.5 1.65 -73 -248 -41.1 1.5 -77.9 -269.7 -47.9 1.4 -80.8 -284.3 -52.4 1.0 -88.6 -344.5 -72.5 0 -93 -502.4 -93 voltage 100mhz (min) 100mhz (max) 66mhz (min) (v) i(ma) i(ma) i(ma) 0 0 0 0 0.4 27.5 70.2 17.7 0.65 41.8 107.5 26.9 0.85 51.6 133.8 33.3 1.0 58.0 151.2 37.6 1.4 70.7 187.7 46.6 1.5 72.9 194.4 48.0 1.65 75.4 202.5 49.5 1.8 77.0 208.6 50.7 1.95 77.6 212.0 51.5 3.0 80.3 219.6 54.2 3.45 81.4 222.6 54.9 -600 -500 -400 -300 -200 -100 0 0 0.5 1 1.5 2 2.5 3 3.5 voltage (v) i (ma) i oh min (66mhz) 66mhz and 100mhz pull-up i oh min (100mhz) i oh max (66 /100mhz) 0 50 100 150 200 250 0 0.5 1 1.5 2 2.5 3 3.5 voltage (v) i (ma) 66mhz and 100mhz pull-down i ol min (100mhz) i ol min (66mhz) i ol max (100mhz)
hy57v281620a rev. 1.0/dec.99 10 v dd clamp @ clk, cke, cs , dqm & dq minimum v dd clamp current v dd (v) i(ma) 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 v ss clamp @ clk, cke, cs , dqm & dq v ss (v) i (ma) -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 0 5 10 15 20 0 1 2 3 voltage ma i (ma) (referenced to v dd ) -60 -50 -40 -30 -20 -10 0 -3 -2.5 -2 -1.5 -1 -0.5 0 voltage ma i (ma) minimum v ss clamp current
hy57v281620a rev. 1.0/dec.99 11 device operating option table hy57v281620a(l)t-6 hy57v281620a(l)t-k hy57v281620a(l)t-h hy57v281620a(l)t-8 hy57v281620a(l)t-p hy57v281620a(l)t-s hy57v281620a(l)t-10 cas latency trcd tras trc trp tac toh 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.4ns 2.7ns 143mhz(7ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns 133mhz(7.5ns) 2clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 2clks 2clks 6clks 8clks 2clks 5.4ns 2.7ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10.0ns) 3clks 3clks 5clks 8clks 3clks 8ns 3ns 83mhz(12.0ns) 2clks 3clks 5clks 8clks 3clks 8ns 3ns 66mhz(15.0ns) 2clks 2clks 4clks 6clks 2clks 8ns 3ns
hy57v281620a rev. 1.0/dec.99 12 command truth table note : 1. exiting self refresh occurs by asynchronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank address, ra = row address, ca = column address, opcode = operand code, nop = no operation command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x h x x x x x l h h h bank active h x l l h h x ra v read h x l h l h x ca l v read with autoprecharge h write h x l h l l x ca l v write with autoprecharge h precharge all banks h x l l h l x x h x precharge selected bank l v burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x self refresh 1 entry h l l l l h x x exit l h h x x x x l h h h precharge power down entry h l h x x x x x l h h h exit l h h x x x x l h h h clock suspend entry h l h x x x x x l v v v exit l h x x
hy57v281620a rev. 1.0/dec.99 13 package information 400mil 54pin thin small outline package 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 22.327(0.8790) 22.149(0.8720) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 1.194(0.0470) 0.991(0.0390) 0.80(0.0315)bsc 0.400(0.016) 0.300(0.012) unit : mm(inch) 0.150(0.0059) 0.050(0.0020)

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